The present invention relates to semiconductor integrated circuits such as microcontrollers.
There are known microcontrollers that receive a high-speed clock output from a high-speed oscillation circuit and a low-speed clock output from a low-speed oscillation circuit and select one of these clocks for use as the current clock. In this type of microcontrollers, the clock can be switched by software during operation, to realize high-speed operation by selecting the high-speed clock or low power consumption by selecting the low-speed clock.
When it is not necessary to use one of the high-speed oscillation circuit or the low-speed oscillation circuit, the unused oscillation circuit is often blocked from connection with an external crystal and the like, to reduce the cost for external components. A microcontroller adopting this method is provided with a circuit for selecting the output of an oscillation circuit in operation as the clock at the time of resetting.
FIG. 9 is a block diagram of a microcontroller including a conventional clock switch device. The clock switch device, denoted by 90, includes a selector 91, a counter 93 and a control register 96. When a reset signal is made active, the control register 96 is reset and outputs “0”. The selector 91 then selects a low-speed clock C2 output from a low-speed oscillation circuit 2 and outputs the selected clock to a CPU 3.
If an external crystal is in connection with a high-speed oscillation circuit 1 and the high-speed oscillation circuit 1 is in operation, the counter 93 overflows after counting up a predetermined number of pulses. By this overflow, the control register 96 is set and outputs “1”. The selector 91 then selects a high-speed clock C1 output from the high-speed oscillation circuit 1 and outputs the selected clock to the CPU 3. If an external crystal is not in connection with the high-speed oscillation circuit 1, the high-speed oscillation circuit 1 does not operate and thus the counter 93 does not overflow. Therefore, the selector 91 continues selecting the low-speed clock C2 output from the low-speed oscillation circuit 2.
After release of the reset, the counter 93 is cleared after the lapse of a fixed time set by a reset delay circuit 9, and the control register 96 is made rewritable. The CPU 3 can now rewrite data in the control register 96 by software to freely switch the selector 91.
The conventional clock switch device described above has the following problem at the time of clock switching by software. That is, after release of the reset, the CPU 3 can freely switch the selector 91 by software. Therefore, the CPU 3 may possibly select a clock output from an oscillation circuit that currently stops oscillating or stops outputting a clock due to non-connection with an external crystal. In such an event, no clock will be supplied to the CPU 3, and this may cause a deadlock.